Not applicable.
The present invention generally relates to integrated circuit (IC) structures and processes that include a strained semiconductor layer. More particularly, this invention relates to a strained silicon layer that is directly on an insulator, yielding a strained silicon-on-insulator (SSOI) structure that is useful for IC device fabrication, such as complementary metal-oxide-semiconductor (CMOS) transistors and other metal-oxide-semiconductor field effect transistor (MOSFET) applications.
Strained silicon CMOS essentially refers to CMOS devices fabricated on substrates having a thin strained silicon (strained-Si) layer on a relaxed SiGe layer. Electron and hole mobility in strained-Si layers has been shown to be significantly higher than in bulk silicon layers, and MOSFET""s with strained-Si channels have been experimentally demonstrated to have enhanced device performance compared to devices fabricated in conventional (unstrained) silicon substrates. Potential performance improvements include increased device drive current and transconductance, as well as the added ability to scale the operation voltage without sacrificing circuit speed in order to reduce the power consumption.
Strained-Si layers are the result of biaxial tensile stress induced in silicon grown on a substrate formed of a material whose lattice constant is greater than that of silicon. The lattice constant of germanium is about 4.2 percent greater than that of silicon, and the lattice constant of a silicon-germanium alloy is linear with respect to its germanium concentration. As a result, the lattice constant of a SiGe alloy containing fifty atomic percent germanium is about 1.02 times greater than the lattice constant of silicon. Epitaxial growth of silicon on such a SiGe substrate will yield a silicon layer under tensile strain, with the underlying SiGe substrate being essentially unstrained, or xe2x80x9crelaxed.xe2x80x9d A structure and process that realize the advantages of a strained-Si channel structure for MOSFET applications are taught in commonly-assigned U.S. Pat. No. 6,059,895 to Chu et al., which discloses a technique for forming a CMOS device having a strained-Si channel on a SiGe layer, all on an insulating substrate.
A difficulty in fully realizing the advantages of strained-Si CMOS technology is the presence of the relaxed SiGe layer under the strained-Si layer. The SiGe layer can interact with various processing steps, such as thermal oxidation, salicide formation and annealing, such that it is difficult to maintain material integrity during the CMOS fabrication, and may ultimately limit the device performance enhancements and device yield that can be achieved. Another disadvantage is that the SiGe layer adds to the total thickness of the body region of the MOSFET. This additional thickness is particularly undesirable for silicon-on-insulator (SOI) FET structures, because it frustrates the ability to form a very thin SOI device, whose merits as a MOSFET structure for very short channel lengths are well documented. Therefore, distinct advantages could be realized with a strained-Si structure that does not include the strain-inducing layer, but instead has a strained-Si layer that is directly on another layer, such as an insulator layer to yield a strained SOI structure. However, conventional wisdom has been that the SiGe layer must be present at all times to maintain the strain in the silicon layer, in that exposure to elevated temperatures during subsequent processing would have the effect of removing the strain in an unsupported strained-Si layer.
The present invention provides a SOI structure and a method for its fabrication, in which a strained silicon layer lies directly on an insulator layer. As such, the invention overcomes the disadvantages of the prior art requirement for strained-Si structures on an insulating substrate to include a strain-inducing (e.g., SiGe) layer between the strained-Si layer and the insulator. The method of this invention generally entails forming a silicon layer on a strain-inducing layer so as to form a multilayer structure, in which the strain-inducing layer has a different lattice constant than silicon so that the strain-inducing layer induces strain in the silicon layer as a result of the lattice mismatch. The multilayer structure is then bonded to a substrate so that an insulating layer is between the strained silicon layer and the substrate, and so that the strained silicon layer directly contacts the insulating layer. For this purpose, the insulating layer may be provided on the substrate or on the surface of the strained silicon layer opposite the strain-inducing layer. The strain-inducing layer is then removed to yield a strained silicon-on-insulator (SSOI) structure that comprises the strained silicon layer on the insulating layer, with the insulating layer being between the substrate and strained silicon layer. As a result, the resulting SSOI structure does not include an additional strain-inducing layer. Instead, the present invention is based on the determination that strain already induced in a silicon layer can be substantially maintained by a substrate that does not have a strain-inducing lattice mismatch with silicon. In the SSOI structure, the insulating layer (alone or in combination with the substrate) is in some manner able to physically inhibit relaxation of the strained silicon layer.
According to the invention, the resulting SSOI structure is particularly well suited as a semiconductor substrate for IC devices. For this purpose, source and drain regions are formed in the surface of the strained silicon layer, and the silicon layer defines a channel between the source region and the drain region. As a result of the method by which the SSOI structure is fabricated, the strained-Si channel directly contacts the insulating layer. By eliminating the strain-inducing layer under the strained-Si channel, the present invention enables the advantages of strained-Si CMOS technology to be more fully realized. For example, eliminating the strain-inducing layer (e.g., SiGe) reduces the total thickness of the MOSFET device, and avoids interactions with various processing steps such that material integrity can be maintained during CMOS fabrication.
Other objects and advantages of this invention will be better appreciated from the following detailed description.